Abstract: We have developed a hardware accelerator for motion planning, a critical operation in robotics. I will present the microarchitecture of our accelerator and describe a prototype implementation on an FPGA. Experimental results show that, compared to the state of the art, the accelerator improves performance by three orders of magnitude and improves power consumption by more than one order of magnitude. These gains are achieved through careful hardware/software co-design. We have modified conventional motion planning algorithms to aggressively precompute collision data, and we have implemented a microarchitecture that leverages the parallelism present in the problem.
Bio: Daniel J. Sorin is the Addy Professor of Electrical and Computer Engineering at Duke University. His research interests are in computer architecture, with a focus on fault tolerance, verification, and memory system design. He is the author of "Fault Tolerant Computer Architecture" and a co-author of "A Primer on Memory Consistency and Cache Coherence." He is the recipient of a SICSA Distinguished Visiting Fellowship, a National Science Foundation Career Award, and Duke's Imhoff Distinguished Teaching Award. He received a PhD and MS in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University.