Mapping High Level Parallel Code to Bespoke Hardware for Energy Efficient and Real Time Autonomous Devices and Smart Sensors.

The two key requirements for real time decision making in robotics systems and smart sensors, is: 1) increased compute power for full AI autonomy, and 2) energy efficiency, which is a a critical concern for long-lasting operation. The goal of this project is to develop novel language processing methodologies, to create low energy custom hardware accelerators with Field Programmable Gate Arrays (FPGAs) from algorithms written in SYCL. SYCL is a portable C++ standard for heterogeneous computing.
Description of the Project: 

**Note: Project availability subject to collaboration agreement being signed**


Codeplay is a company in Edinburgh with industry expertise with compiler construction and processor architectures. They are a leading partner in the standardisation of SYCL, a programming abstraction for heterogeneous hardware. Codeplay have SYCL implementations for CPUs and GPUs.

The Codeplay CEO, Andrew Richards, founded the company in 2002. He chairs the working group for the SYCL standard within the Khronos Group.


Computing platforms for robotics, smart sensors, and remote autonomous AI are constructed from diverse computing components with diverse performance and power requirements. A typical platform combines multicore CPUs/GPUs and, increasingly, FPGAs for specialised close-to-sensor processing.

The performance metric for a particular autonomous robotics system may be accuracy, latency, energy use, throughput, or any combination of these. To meet these requirements, a major challenge is the seamless realisation of some given computation across different configurations of processing components. This is made harder by major differences in programming models for such components and the lack of common abstractions and toolsets.

In particular, FPGAs are very low powered accelerated processors, which are ideal for remote computation where access to power and network connectivity is limited, e.g. where autonomously deployed devices and sensors cannot transmit raw data. Application areas exploitable with FPGAs include smart CCTV surveillance, autonomous vehicles and medical diagnosis.

The major drawback of FPGAs is programmability. They are notoriously difficult and time consuming to engineer and debug, holding back their wider adoption with the software industry, roboticists, and manufacturers of heterogeneous processing hardware.

This PhD project, supported by Codeplay and the Robotics and Autonomous Systems CDT, will address this challenge by combining Heriot-Watt University's programming language and FPGA research, with Codeplay's architectures and compilers expertise.

In particular, in Heriot-Watt University's EPSRC Rathlin project (EP/K009931/1) we developed an image processing language and  program transformations to improve the throughput and energy efficiency of FPGAs. These approach will be taken across to Codeplay's OpenCL toolsets.

The RAS-CDT PhD student will work with Codeplay on an FPGA implementation of the SYCL open standard. Codeplay's image processing DSL, VisionCPP, will serve as an excellent case study for demonstrating high level programming for parallel image processing on heterogeneous platforms, in particular on low powered FPGAs via the proposed SYCL FPGA backend.

This project presents significant commercialisation potential for Codeplay, and offers opportunities for a good student to publish high impact publications on programming language design, optimisations using compiler based domain specific rewrite rules, and optimisations for heterogeneous platforms using machine learning techniques.

For Codeplay, the commercial output of this project is a demonstration and evaluation of using C++ programming techniques to deliver performance portability of embedded intelligence algorithms on FPGAs and other heterogeneous systems. This will help Codeplay deliver and market C++ programming models for FPGAs and other accelerators. The currently available C++ standard for heterogeneous processors is SYCL, which Codeplay has an implementation of. This may start to migrate towards the full ISO C++ standard. The research in this project should help push those standards forwards. The work in the project, to be commercially relevant, should be as much as possible a collaboration between Heriot-Watt University, Codeplay and Xilinx (an FPGA company). Xilinx are working on their own FPGA implementation of SYCL and are very involved in the standardization efforts.

This PhD project will be a good collaborative fit for the Innovate UK WIZER battery project between Codeplay, Williams Advanced Engineering and Imperial College London.


Project number: 
First Supervisor: 
Heriot-Watt University
First supervisor university: 
Heriot-Watt University
Essential skills and knowledge: 
Parallel computing, programming languages, compilers.
Desirable skills and knowledge: 
Parallel and heterogeneous processor architectures, FPGAs, hardware cost models, code profiling.
Industry placement details: 
Work placement at Codeplay. Floor C, Argyle House, 3 Lady Lawson St, Edinburgh EH3 9DR.